In a wafer-level chip packaging structure, the integrated devices, such as transistors, etc., are formed on semiconductor substrate firstly; and then metal interconnect structures are formed on the integrated devices. Further, soldering pads are formed on the metal interconnect structures to electrically connect with the metal interconnect structure. Further, soldering balls are formed on the soldering pads to electrically connect the integrated devices with a printed circuit board (PCB), or electrically connect the packaging structures of a plurality of other chips.
In a practical fabrication process, when a packaging structure is connected with a PCB and/or another packaging structure, in order to avoid a short circuit between adjacent soldering pads caused by the melting of soldering balls, it requires that the adjacent soldering pads should have a certain distance. Such a distance may reduce the density of the soldering pads, and the device density on the substrate is reduced as well. In order to solve the low device density problem, a metal pillar technology has been developed. The metal pillar technology refers to a technology that forms metal pillar bump structures, i.e., metal pillars with a relatively large thickness, on the soldering pads. The metal pillar bump structures extend the distance between corresponding soldering pads on the chip packaging structures; and/or the distance between pins of the PCB and the soldering pads on the chip packaging structures. Thus, when the soldering balls are melted, the liquid soldering balls may not flow onto the adjacent soldering pads to cause a short circuit. By using metal pillar bump structures, the device density on the substrate may be increased.
However, the thickness of the meal pill bump structures is relatively large; and the relatively large thickness of the pillar bump structures may cause the pillar bump structures to have a significantly large stress. When high temperature processes are used in the fabrication and packaging of the chips, the stress in the pillar bump structures may cause the dielectric layer on the semiconductor substrate to break, thus the reliability of the chip packaging structures may be relatively low; and the devices may fail. In order to solve the stress problem, a polyimide layer may be formed on the soldering pads to be used as a stress buffer layer, but a polyimide etching process has to be used, thus the production cost and the packaging time are increased. The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.